Password Management: Create a secure password management system that automatically strengthens a 'weak' user password for each domain. All of which is authorized and secured using one private master password.
Charge Trap-based Camouflage Gates (CTCG) for Reverse Engineering Prevention: Propose a CTCG which are resilient towards various RE attacks, without requiring a process change in realizing them.
Robust & Energy-Efficient Domain Wall Caches: Exploit the trade-off between power and performance by address-based and work-load based cache monitoring.
Layout Design of the Memory controller: Designed and tested (LVS, DRC) of a memory controller used in a STTRAM sensing circuit. (was a collaborative effort with my colleagues from our Lab).
SPA-Based attack on DES Encryption: Crack the encryption key through a Trojan based side channel attack.
Design of low-power ALU with wide operating range: Optimizing circuit design to sustain high performance at low power.
Safety System for a Semi-Automatic Robot (January-May 2010): Create a safety device for a human controlled robot that is capable of working in an obstacle-filled terrain.
Huffman Encoder: Characters were assigned a bit size depending on their frequency of occurrence, using Verilog HDL.
Micro- UART: Design of the Universal Asynchronous Receiver and Transmitter in Verilog HDL.
AMBA APB Protocol: Data management, control, transmission & reception using Sys Verilog.
